IEEE Solid-State Circuits Magazine - Winter 2016 - 58

Table 3. a comparison of sc volTage mulTipliers.

Ladder

VCAP /VIN

VDIO /VIN

#serial cap

# inpuT Terminal

impacT of C_para

N/2

Brugler

+++

Falkner and
Dickson

Parallel

N+1

Ueno

Fibonacci

F(N−2)

F(N−1)

N/2

+++

Relative Circuit Area

FIB2

4
3
2
1
0

3x2

N−2

4
6
Voltage Gain

Relative Power Efficiency

Cernea

N−1

FIB2

1.0
0.8
0.6
0.4
0.2
0.0

(a)

4
6
Voltage Gain

(b)

Figure 9: multiplier area versus parasitic capacitance [17].

of voltage multipliers. The upper
side of Figure 8(b) shows a first half
period when I OUT = 0. The upper
stages are connected in series with
the output terminal, whereas the
lower stages are connected in parallel with the upper stages. As the
number of stages increases by one,
the maximum attainable voltage
increases by a factor of two in an
ideal case where no parasitic capacitance is considered. You may consider the number of stages of the
2 N multiplier to be smaller than
that of the Fibonacci voltage multiplier. But that's not the case because
the 2 N voltage multiplier needs two
arrays. Capacitors and diodes need
to be high-voltage devices.

Comparison of Voltage Stress
on Devices and Impact
of Parasitic Capacitance
Table 3 summarizes the characteristics of each SC voltage multiplier
[15], [16]. The CW and SP multipliers can be composed of low-voltage

W I N T E R 2 0 16

capacitors, but the number of serially connected stages is large and the
number of input terminals is small.
As a result, the impact of parasitic
capacitance (C_para) is significant.
On the other hand, the Falkner and
Dickson parallel multiplier has less
impact of parasitic capacitance on
charge transfer because the number
of serially connected stages is small
and the number of input terminals
is large. Ueno Fibonacci/Cernea 2 N
cells can have a fewer number of
capacitors than the others, but half
to all capacitors are connected in
serial, resulting in a significant loss
in voltage gain due to the high sensitivity of parasitic capacitance.

Best Topology for Integrated
Voltage Multiplier
To identify the best topology for integrated voltage multiplier especially
whose voltage gain is more than a
few, the area and power efficiency
of each topology cell are quantitatively compared one another. The

IEEE SOLID-STATE CIRCUITS MAGAZINE

required area and resultant power
efficiency of SP, Fibonacci (FIB2),
and 2 N (2 N) cells are normalized
by those of Falkner-Dickson parallel
cell in Figure 9 [17]. All the capacitors in a cell are assumed to be
uniform except for FIB2, where the
k th stage capacitor size is made
proportional to Fibonacci number of
(N - k) . In a typical CMOS process,
the top and bottom plate parasitic
capacitance can be as large as 10%
of the multiplier capacitor including
the parasitic capacitance of wiring
and switching devices. Each multiplier is designed to have the same
output current with the same clock
frequency. As seen in Figure 9(a),
any cell needs larger circuit area
than the parallel cell for a voltage
gain greater than three. The power
efficiency in Figure 9(b) has a similar trend as does the area. As the
number of multiplier capacitors
needs to be increased, more power
needs to drive the parasitic capacitance, which results in lower power
efficiency. As a result, the FalknerDickson parallel multiplier should
be selected for integration with
respect to area and power.
Figure 10 shows more evidence
about the best topology for integration across the voltage gain in
literature. I and D , respectively,
indicate integrated and discrete.
Two designs have been realized with
Cockcroft-Walton cells for earphone
to have a voltage gain of five with
no high-voltage devices [18], [19].
There have been some designs with
SP and Fibonacci cells that have voltage gains higher than five but either
has needed discrete capacitors and

Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Winter 2016