IEEE Solid-State Circuits Magazine - Winter 2016 - 6

c ircu it intu itions

Ali Sheikholeslami

Offset Cancellation

Welcome to the eighth article in this
"Circuit Intuitions" column series.
As the title suggests, each article
provides insights and intuitions into
circuit design and analysis. These
articles are aimed at undergraduate
students but may serve the interests
of other readers as well. If you read
this article, I would appreciate your
comments and feedback, as well as
your requests and suggestions for
future articles in this series. Please
send your comments to me at ali@
ece.utoronto.ca.
In a previous article, "Process
Variation and Pelgrom's Law," we
presented the concept of offset voltage of an amplifier and how it could
be reduced by using larger transistors. However, there is a cost associated with doing that. An obvious
cost is the silicon area; others are
the impacts of large transistors on
speed and power consumption. In
this article, we review two techniques known as "auto-zero" to either cancel the offset altogether or
substantially reduce it. We begin by
reviewing the adverse effects of offset voltage, when not cancelled.
Figure 1 shows how an op-amp
with a non-zero input offset voltage
can be modeled as an op-amp with
zero offset voltage in series with a
dc voltage source (VOS) at its input
terminal. The value of VOS is not
known before fabrication, although
it is known that it can be represented
by a random variable with Gaussian
distribution. For example, consider
an amplifier with a gain of 200 using
Digital Object Identifier 10.1109/MSSC.2015.2495818
Date of publication: 21 January 2016

W I N T E R 2 0 16

Ideal Op-Amp
(Zero Offset)

Vos
- +

Vin

Vout

Non-Ideal Op-Amp
(with Non-Zero Offset)
Figure 1: An amplifier with an input
offset voltage of VOS can be modeled as
an ideal op-amp (i.e., one with zero input
offset voltage) in series with a dc voltage
source VOS .

±1-V power supply. If there is no offset in this amplifier (i.e., if VOS = 0
), then the amplifier can take in an
input voltage as large as 5 mV (peak)
to produce a 1-V (peak) output. On
the other hand, if we assume there
is an input offset voltage of 3 mV,
then for a 0-V input, the output is
already at 0.6 V, leaving only 0.4 V

+
-

- + +
A
-

Vo1 Co Vout
+

-
AVos

(a) Auto-Zero Phase

+
Vin
-

- + +
A
-

Vo1

Co V
out

+ AV -
os

(b) Operation Phase

Figure 2: The auto-zero technique to cancel offset with the aid of a capacitor at the
output of the amplifier. In (a) the auto-zero
phase, the capacitor is charged to AVOS,
and in (b) the operation phase, the voltage
across the capacitor cancels the effect of
input offset voltage.

IEEE SOLID-STATE CIRCUITS MAGAZINE

(peak) for the output signal before
the output voltage saturates at 1
V. This translates to a peak input
amplitude of 2 mV only! At an offset
voltage of 5 mV or higher, the output
voltage of the amplifier will saturate
even with zero input voltage, rendering the op-amp useless.
What makes the situation complicated is that the offset is not known
a priori; if we replicate an amplifier
ten times on the same die, each of
them will end up with a different
offset voltage. So how can we compensate for the offset voltage?
One idea is to measure the offset
voltage after the amplifier is fabricated and store it on a capacitor. We
can then subtract the stored value
from the original offset by placing
the two components in series (with
appropriate polarity). Let us review
two methods of doing this, both
called the auto-zero technique.
Figure 2 places a capacitor (C O)
in series with the output node of the
amplifier. In Phase I of the operation,
called the auto-zero phase, we short
the input terminals together (so as to
create zero input voltage) and ground
the floating terminal of the capacitor [see Figure 2(a)]. By doing so, the
amplifier will generate an output voltage AVOS, which will be stored on
the capacitor. In Phase II, called the
operation phase, we remove the short
from the input terminals and disconnect ground from the output terminal
[see Figure 2(b)]. We then connect the
input signal to the input terminals
and observe the output at the floating
terminal of the capacitor. If the input
offset voltage is small enough, so as
not to saturate the voltage at node

Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Winter 2016