IEEE Solid-State Circuits Magazine - Winter 2016 - 61
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the application of optimization
methods to the design of electrical
systems by using field and circuittheory tools and signal processing
the development of effective numerical methods of the analysis of
the electromagnetic fields by applying finite element and boundary
elements in two- and three-dimensional electromagnetic and coupled
problems
the development of new effective
methods for the solution of specific
biomedical problems, electronics,
telecommunication, and antenna
systems
the development of efficient methods of signal processing based on
the application of ICA, PCA, wavelet transformation, and impedance
tomography.
artificial neural and neuro-fuzzy network approaches to the solution of
signal processing tasks belonging to
the estimation, identification, prediction, and approximation of problems
modern problems of solid-state
circuits theory and application
education in the area of electrical
engineering, computer science, and
the application of computer science.
The following papers were presented
at the CPEE plenary session:
■ "Positivity and Stability of DiscreteTime and Continuous-Time Nonlinear Systems" by Tadeusz Kaczorek
(Poland)
■ "Features of an eLearning Software
for Teaching and Self-Studying of
Electrical Engineering" by Yuriy
Bobalo, Petro Stakhiv, and Natalya
Shakhovska (Ukraine)
■ "Open Access System for Radiotherapy Planning" by Jacek Starzyn´ski,
Robert Szmurło, Bartosz Chaber,
and Zuzanna Krawczyk (Poland)
■ "The Influence of Parameters of
Evolutionary Selection of Model
Form on its Precision and Complexity" by Liliana ByczkowskaLipin´ska, Petro Stakhiv, and Yuriy
Kozak (Poland and Ukraine).
The conference's social program
included a tour of the main building of
Lviv Polytechnic National University,
the oldest technical higher educational
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institution in Ukraine and East Europe.
The CPEE participants had a series of
walking and bus tours around the Lviv
city center that gathered everyone in a
friendly, relaxed, and warm atmosphere
of the ancient downtown of Lviv.
The CPEE dates back to 1999
when it started as a joint UkrainianPolish electrical engineering seminar. The idea to organize such a
conference belonged to the Department of Theoretical and Electrical Engineering of Lviv Polytechnic
National University and the Institute
of Theory of Electrical Engineering,
Measurement, and Information Systems of the Warsaw University of
Technology. Now, CPEE is an international, highly scientific conference.
-Dr. Mykhaylo I. Andriychuk
IEEE MTT/ED/AP/CPMT/SSC West
Ukraine Chapter
-Dr. Oksana Hoholyuk
Secretary of CPEE 2015
Organizing Committee
Server Processors, Specialized High-Performance Chips,
and Deep Learning Were Highlights at the 2015 Hot Chips Conference
T
The 2015 Hot Chips Conference was
held at the Flint Center for the Performing Arts in Cupertino, California,
on 23-25 August 2015. The conference highlighted the outlook for several promising developments ranging
from new server processors to field
programmable gate arrays (FPGAs),
graphics processing unit (GPUs), and
graphics chips. Specialized applications such as the Internet of Things
and mobile chips were discussed as
well. Two outstanding keynote talks
were also presented. The first talk
was on convolutional neural networks, an area that has had dramatic
Digital Object Identifier 10.1109/MSSC.2015.2495860
Date of publication: 21 January 2016
breakthroughs in the last couple of
years in the field of deep learning
with applications to big data analytics
and image classification such as facial
recognition. The second keynote talk,
on the growth of a unified air interface for 5G cellular communication,
showed a rapidly expanding area of
opportunity for improved channel
and connection management.
Knights Landing: Second
Generation Intel Xeon Phi Processor
The 200-W Knights Landing (KNL)
xeon phi processor from Intel is targeted at high performance computing
and supercomputing by integrating
72 Silvermont-derived cores with four
threads each. Integrated on package
are up to 16 GB of stacked-die multichannel DRAM (MCDRAM) with a
bandwidth of 400 GB/s, which can be
configured as either cache, memory,
or both. In addition, the Omni-Path
fabric is also integrated on package,
providing low-latency and higher
bandwidth interconnect of 200 Gb/s/
direction. Six channels of DDR 2400
at a total bandwidth of 90 GB/s access
up to 384 GB of memory.
Intel Xeon Processor D: The First
Xeon Processor Optimized
for Dense Solutions
Accompanying the KNL presentation
was the 14-nm Xeon-D processor. Optimized for 2.4x the performance/watt
as Broadwell and a dense form factor,
IEEE SOLID-STATE CIRCUITS MAGAZINE
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Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Winter 2016
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