IEEE Solid-State Circuits Magazine - Winter 2016 - 62

Tile
Knights Landing Overview

EDC

PCIe
Gen 3

EDC

36 Tiles
Connected by
2-D Mesh
Interconnect

EDC

DDR MC

Misc

EDC

MCDRAM
MCDRAM

Package

EDC

CHA
1 MB
L2

2 VPU
Core

Chip: 36 Tiles Interconnected by 2-D Mesh
Tile: 2 Cores + 2 VPU/Core + 1 MB L2

EDC

Tile

DDR MC

Core

×4
MCD RAM
DMI
MCDRAM

Memory: MCDRAM: 16 GB On-Package; High BW
DDR4: 6 Channels at 2,400 up to 384 GB

3 DDR4 Channels

3 DDR4 Channels

EDC

2 × 16
1×4

DMI

MCDRAM
MCDRAM

2 VPU

IO: 36 Lanes PCIe Gen3. 4 Lanes of DMI for Chipset
Node: 1-Socket Only
Fabric: Omni-Path On-Package (Not Shown)

Vector Peak Perf: 3 + TF DP and 6 + TF SP Flops
Scalar Perf: ~3× Over Knights Corner
Streams Triad (GB/s): MCDRAM: 400+; DDR: 90+

EDC

MCDRAM
MCDRAM

Omni-Path Not Shown
KNL showing the mesh-connected 36 tiles and the MCDRAMs integrated on the package.

Servers

Scalable Unified Storage Solution
* Entry Solutions Are TDP Constrained
- Xeon D TDP Range (20-45 w) Critical

Switches

PCIe
SAS
SAS IOC

Canister
B
PCIe

Intel
Xeon D
SAS SAS IOC
SAS

SAS
SAS EXP

SAS EXP

- PCIe NTB, DMA Engine Enable Higher
Availability
- ADR Feature for RAID Cache Data
Protection

NVM
SAS

4x 4x

4x 4x

NVM

PCIe NTB

DDR4 DDR4

Intel
Xeon D

Host
IOCs

DDR4 DDR4

Storage
Platform

Host
IOCs
PCIe

PCIe NTB

Canister
A

* Integrated Storage Extensions
Fundamental to the Solution

- PCIe Dualcast Reduces Memory BW
Demand
- Integrated Ethernet Used as the Host
Interface or for Clustering
* ISA for Data Protection, Storage
Efficiency, and Management
- RAID-5/6, CRC, Encryption, Hashing,
and Compression

SSD: High-Performance Storage
SAS: Enterprise Performance Storage
SATA: Enterprose Bulk Storage
Xeon-D: enterprise storage example with dual canister flow.

it features an integrated 10-GbE Ethernet with two ports. DDR4 interfaces
provide 2400 MT/s. Other features include support for virtualization, cache
allocation, cache monitoring, and memory bandwidth monitoring.

62

W I N T E R 2 0 16

Oracle's Sonoma Processor:
Advanced Low-Cost SPARC
Processor for Enterprise Workloads
Sonoma, Oracle's low-cost form
factor SPARC processor, is optimized for scale-out and features an

IEEE SOLID-STATE CIRCUITS MAGAZINE

integrated infiniband-host channel
adapter with virtualization, four
direct attached DDR4-2400 channels
supporting up to 1 TB of memory,
and advanced software-in-silicon
hardware features optimized for



Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Winter 2016

IEEE Solid-State Circuits Magazine - Winter 2016 - Cover1
IEEE Solid-State Circuits Magazine - Winter 2016 - Cover2
IEEE Solid-State Circuits Magazine - Winter 2016 - 1
IEEE Solid-State Circuits Magazine - Winter 2016 - 2
IEEE Solid-State Circuits Magazine - Winter 2016 - 3
IEEE Solid-State Circuits Magazine - Winter 2016 - 4
IEEE Solid-State Circuits Magazine - Winter 2016 - 5
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IEEE Solid-State Circuits Magazine - Winter 2016 - 9
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IEEE Solid-State Circuits Magazine - Winter 2016 - 18
IEEE Solid-State Circuits Magazine - Winter 2016 - 19
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IEEE Solid-State Circuits Magazine - Winter 2016 - 22
IEEE Solid-State Circuits Magazine - Winter 2016 - 23
IEEE Solid-State Circuits Magazine - Winter 2016 - 24
IEEE Solid-State Circuits Magazine - Winter 2016 - 25
IEEE Solid-State Circuits Magazine - Winter 2016 - 26
IEEE Solid-State Circuits Magazine - Winter 2016 - 27
IEEE Solid-State Circuits Magazine - Winter 2016 - 28
IEEE Solid-State Circuits Magazine - Winter 2016 - 29
IEEE Solid-State Circuits Magazine - Winter 2016 - 30
IEEE Solid-State Circuits Magazine - Winter 2016 - 31
IEEE Solid-State Circuits Magazine - Winter 2016 - 32
IEEE Solid-State Circuits Magazine - Winter 2016 - 33
IEEE Solid-State Circuits Magazine - Winter 2016 - 34
IEEE Solid-State Circuits Magazine - Winter 2016 - 35
IEEE Solid-State Circuits Magazine - Winter 2016 - 36
IEEE Solid-State Circuits Magazine - Winter 2016 - 37
IEEE Solid-State Circuits Magazine - Winter 2016 - 38
IEEE Solid-State Circuits Magazine - Winter 2016 - 39
IEEE Solid-State Circuits Magazine - Winter 2016 - 40
IEEE Solid-State Circuits Magazine - Winter 2016 - 41
IEEE Solid-State Circuits Magazine - Winter 2016 - 42
IEEE Solid-State Circuits Magazine - Winter 2016 - 43
IEEE Solid-State Circuits Magazine - Winter 2016 - 44
IEEE Solid-State Circuits Magazine - Winter 2016 - 45
IEEE Solid-State Circuits Magazine - Winter 2016 - 46
IEEE Solid-State Circuits Magazine - Winter 2016 - 47
IEEE Solid-State Circuits Magazine - Winter 2016 - 48
IEEE Solid-State Circuits Magazine - Winter 2016 - 49
IEEE Solid-State Circuits Magazine - Winter 2016 - 50
IEEE Solid-State Circuits Magazine - Winter 2016 - 51
IEEE Solid-State Circuits Magazine - Winter 2016 - 52
IEEE Solid-State Circuits Magazine - Winter 2016 - 53
IEEE Solid-State Circuits Magazine - Winter 2016 - 54
IEEE Solid-State Circuits Magazine - Winter 2016 - 55
IEEE Solid-State Circuits Magazine - Winter 2016 - 56
IEEE Solid-State Circuits Magazine - Winter 2016 - 57
IEEE Solid-State Circuits Magazine - Winter 2016 - 58
IEEE Solid-State Circuits Magazine - Winter 2016 - 59
IEEE Solid-State Circuits Magazine - Winter 2016 - 60
IEEE Solid-State Circuits Magazine - Winter 2016 - 61
IEEE Solid-State Circuits Magazine - Winter 2016 - 62
IEEE Solid-State Circuits Magazine - Winter 2016 - 63
IEEE Solid-State Circuits Magazine - Winter 2016 - 64
IEEE Solid-State Circuits Magazine - Winter 2016 - 65
IEEE Solid-State Circuits Magazine - Winter 2016 - 66
IEEE Solid-State Circuits Magazine - Winter 2016 - 67
IEEE Solid-State Circuits Magazine - Winter 2016 - 68
IEEE Solid-State Circuits Magazine - Winter 2016 - 69
IEEE Solid-State Circuits Magazine - Winter 2016 - 70
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IEEE Solid-State Circuits Magazine - Winter 2016 - 88
IEEE Solid-State Circuits Magazine - Winter 2016 - Cover3
IEEE Solid-State Circuits Magazine - Winter 2016 - Cover4
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