Package Lid Package Substrate XCVR (6CH) XCVR (6CH) XCVR (6CH) XCVR (6CH) XCVR (6CH) AIB AIB XCVR (6CH) Core Fabric Pcle × 16 AIB XCVR (6CH) AIB Pcle × 16 XCVR (6CH) XCVR (6CH) XCVR (6CH) XCVR (6CH) XCVR (6CH) XCVR (6CH) XCVR (6CH) AIB XCVR (6CH) AIB XCVR (6CH) Pcle × 16 AIB XCVR (6CH) AIB Pcle × 16 XCVR Tile 24 XCVRs PCIe HIP 3V GPIO Pcle × 16 AIB XCVR (6CH) AIB XCVR (6CH) AIB AIB Pcle × 16 XCVR (6CH) XCVR (6CH) XCVR (6CH) XCVR (6CH) XCVR (6CH) XCVR (6ch) Transceiver Banks Intel EMIB HyperConnect-AIB AIB Pcle × 16 PCIe Hard IP Block Note: Not to Scale 27 13 11 11 224 Input Image (RGB) 224 3 Stride of 4 5 3 27 3 5 55 96 256 Maximum Pooling 3 13 3 384 13 3 3 384 13 Maximum Pooling 3-D Convolution and Maximum Pooling 13 Dense Input Dense 55 Dense A 3-D system-in-package construction showing the Intel embedded multidie interconnect bridge connecting the core fabric die to the six XCVR die. Output 13 256 1,000 Maximum 4,096 4,096 Pooling "Dog" Dense Layers An image recognition using deep CNNs. through-silicon vias, which is limited to one reticle in size. Deep Learning and Convolutional Neural Networks Convolutional neural networks (CNNs) have achieved huge breakthroughs in implementing deep learning for applications such as facial recognition and 64 W I N T E R 2 0 16 image classification voice recognition. This has been done in the past on central processing unit-based servers and GPUs, but emphasis is shifting to FPGAs and application-specified integrated circuits. Eric Chung of Microsoft Research described using FPGAs compared to GPUs for deep learning and implementing convolutional neural networks. IEEE SOLID-STATE CIRCUITS MAGAZINE Yann LeCun of Facebook gave the keynote on CNNs (Convnets), describing their widespread applications, particularly for big data analytics. The next steps are to integrate reasoning with deep learning, develop a good architecture for episodic (short-term) memory, and find good principles for unsupervised learning.