IEEE Solid-State Circuits Magazine - Winter 2016 - 68

IEEE EDS/SSCS Bangalore Chapter Hosts Mini Colloquium

The IEEE Electronic Devices Society
(EDS) and Solid-State Circuits Society (SSCS) Bangalore Chapter hosted
an interactive mini colloquium
with three Distinguished Lecturers
(DLs): Dr. Souvik Mahapatra Distinguished Lecturer, EDS, Indian Institute of Technology (IIT), Bombay,
India; Dr. Shanthi Pavan, DL, SSCS,
IIT, Chennai, India; Dr. Ram Krishnamurthy, DL, SSCS, Intel, Oregon,
United States.
The mini colloquium was inaugurated with a talk by Dr. Souvik
Mahapatra, "Macroscopic and Stochastic Aspects of Negative Bias
Temperature Instability in Sub20-nm Devices and Circuit." The talk
dealt with mechanisms of negativebias temperature instability and its
effect on circuits. This is a crucial
reliability concern for modern day
state-of-the-art CMOS technologies.
The session was very well received
by the audience.
Dr. Mahapatra's talk was followed
by Dr. Shanthi Pavan's presentation,
"Low Power Continuous-Time Delta
Sigma Converters." This talk covered all of the key aspects of sigma
delta analog and digital converters (ADC), from the very basics to
advanced concepts. The talk highlighted techniques that are used to
reduce power dissipation with interesting design examples of several
state-of-the-art ADCs.
The final session was a talk by
Dr. Ram Krishnamurthy, "EnergyEfficient Circuit Technologies for the
Sub-14-nm Era: Challenges and Opportunities." He presented some of
Digital Object Identifier 10.1109/MSSC.2015.2495880
Date of publication: 21 January 2016

W I N T E R 2 0 16

(From left) DLs souvik Mahapatra, shanthi pavan, and ram Krishnamurthy gave presentations at the sscs Bangalore chapter's mini colloquium.

The mini colloquium
was inaugurated
with a talk by Dr.
Souvik Mahapatra.

the prominent barriers to designing
energy-efficient circuits in the sub14-nm CMOS technology regime and
outlined new paradigm shifts necessary in next-generation multi-core
microprocessors and systems-on-achip (SoCs). He has also talked about
emerging trends and key challenges
in sub-14-nm design, including device and on-chip interconnect technology projections, performance,
leakage and voltage scalability, special-purpose hardware accelerators
and reconfigurable coprocessors for
compute-intensive signal processing algorithms, fine-grain power

IEEE SOLID-STATE CIRCUITS MAGAZINE

management with integrated voltage
regulators, and resilient circuit design
to enable robust variation-tolerant operation. Dr. Krishnamurthy discussed
the review conducted on power-efficient optimization of microprocessors to span a wide operating range
across high-performance servers to
ultra-mobile SoCs, dynamic on-the-fly
configurability and adaptation, and
circuit techniques for active/standbymode leakage reduction with robust
low-voltage operability. He concluded
his talk with specific chip design examples and case studies.
The mini colloquium was very
well received by the audience, including IBM researchers, students, and
professors from various Bangalorebased colleges.
-Janakiraman Viraraghavan
Bangalore Chapter Chair

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