IEEE Solid-State Circuits Magazine - Winter 2016 - 79

SSCS-Macau Chapter Organizes the
2015 Advanced IC Design Workshop Series

The IEEE Solid-State Circuits Society
(SSCS)-Macau Chapter held a joint
workshop with the State Key Laboratory (SKL) of Analog and Mixed-Signal VLSI of the University of Macau.
The Advanced IC Design Workshop
Series was held 15-16 June and
13-14 July 2015. The workshops
featured seven Distinguished Lecturer sessions that were delivered
by three well-known experts who
shared information on advanced
analog and mixed-signal IC design
technology with a focus on data
converters and wireless circuits and
systems. Smart sensors, which is
a key active research area that the
Macau solid-state circuits designers
have been engaging in, was also a
topic of focus. The workshops were
very successful and attracted 40-50
attendees for each session, ranging
from academia faculties, researchers and students from the University of Macau and also industrial
analog and mixed-signal R&D engineers from Synopsys Macau Ltd. The
SSCS-Macau Chapter and the SKL of
the University of Macau have organized this kind of workshop every
year to serve as an excellent forum
for presenting, exchanging, and discussing the most updated circuit
techniques, ideas, and trends for the
state-of-the-art analog and mixedsignal IC design among lecturers
and local IC researchers/designers.
At the workshop held on 15-16
June, Prof. Behzad Razavi from the
University of California, Los Angeles, delivered lecture sessions for
the following topics.

prof. Behzad razavi presented at the advanced Ic Design Workshop series in June 2015.

shown great promise for low-power
design. The speed of SAR architectures
can be improved through the use of
interleaving or multibit conversion,
each posing its own tradeoffs. Specifically, multibit schemes employ several
digital-to-analog converters, incurring a large area penalty and a high
input capacitance.
This presentation proposes the
use of voltage-controlled oscillators
(VCOs) as multibit quantizers in a
SAR environment. Resolving 3 bits
per cycle, this approach also allows
shorter least significant bit conversion times by adjusting the VCO gain
on the fly. A 40-nm CMOS prototype
incorporates two VCOs and a timeto-digital converter (TDC) along with
background calibration to achieve
an SNDR of 68 dB and a figure of
merit of 8 fJ/conv. step at Nyquist.

A 12-Bit 200-MS/s 3.4-mW ADC

Channel Selection at RF

Successive approximation register (SAR)
analog-to-digital converters (ADCs) have

A holy grail in RF design has been
to perform channel selection at RF,
i.e., to remove strong interferers
and even out-of-channel noise at the
receiver input. Such an approach is

Digital Object Identifier 10.1109/MSSC.2015.2495889
Date of publication: 21 January 2016

attractive because it greatly relaxes
the linearity requirements of the
receiver chain, ultimately leading to
a lower power consumption and a
more compact design.
This research demonstrates a universal CMOS receiver employing RF channel selection and meets the exacting
demands of GSM and WCDMA. Drawing
upon computated networks, we introduce the concept of the Miller bandpass
filter and several of its variants so as to

prof. Kofi Makinwa presented various topics at the advanced Ic Design Workshop
series in July 2015.

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