IEEE Solid-State Circuits Magazine - Winter 2016 - 80

"Micropower ADCs"
With the current trend toward increasingly autonomous systems, micropower ADCs have become critical
components. In this presentation, the
basic principles of micropower SAR
and sigma-delta ADCs will be discussed. It shows how these two proven
techniques can be combined to realize
high resolution micropower ADCs.
At the workshop held on 13-14
July, Prof. Borivoje Nikolic´ from the
University of California at Berkeley
delivered the following talks.

"xG: 5G and Beyond"
prof. Borivoje Nikolic´ delivered engaging lectures at the advanced Ic Design Workshop
series in July 2015.

create a receiver that achieves a narrow
channel bandwidth and can withstand
large blockers. Realized in 65-nm technology, the prototype provides a programmable bandwidth from 350 kHz
to 20 MHz and draws 20 mW. The noise
figure is 2.9 dB in the absence of blockers and 5 dB with a 0-dBm blocker at
20-MHz offset.

in the performance and the increase
in the complexity as higher resolutions are sought. The state-of-the-art
examples are finally presented.
At the workshop held on 13-14
July, Prof. Kofi Makinwa from the
Delft University of Technology delivered the following talks.

All-Digital PLLs

"Designing Smart Sensors in
Standard CMOS"

All-digital phase-locked loops (ADPLLs)
have recently become popular as they
offer certain advantages over their
analog counterparts. While the term
all-digital is a misnomer, ADPLLs do
simplify certain aspects of the design. This presentation describes
the evolution from the analog PLLs
to ADPLLs, identifying the DCO and
the TDC as the design bottlenecks.
Various TDC topologies are studied,
and the effect of TDC quantization is
formulated. Several state-of-the-art
examples, including TDC-less architectures are presented.
DCOs are an integral component
in ADPLLs, posing interesting and difficult challenges in the design. This
presentation next introduces DCO performance parameters and describes
basic DCO topologies, and then the
tuning and resolution issues and views
the DCO as a digital-to-frequency converter. Next, the digital control of ring
oscillators and LC oscillators are studied with emphasizing the degradation

Sensors are everywhere! Temperature
sensors throttle systems-on-a-chip,
accelerometers activate airbags, and
magnetic field sensors form the basis
of electronic compasses. These are all
examples of smart sensors, i.e., sensors that are cointegrated with their
readout electronics and so provide
digital output. However, processing
the weak analog output of typical sensors is quite challenging, especially
when it must be done in standard
CMOS whose precision is limited by
1/f noise, component tolerances, and
mismatch. A system approach to the
design of smart sensors is presented.
The use of dynamic techniques such
as chopping, auto-zeroing, dynamic
element matching, and sigma-delta
modulation to trade speed for precision are also discussed. The proposed methodology is illustrated by
case studies describing the design of
state-of-the-art CMOS sensors for the
measurement of wind velocity, magnetic field, and temperature.

W I N T E R 2 0 16

IEEE SOLID-STATE CIRCUITS MAGAZINE

This talk presents the recent research
results from the Berkeley Wireless
Research Center and presents the
vision for the development of wireless in the next decade. To support
this vision, we have been developing
technologies that are considered the
cornerstones of fifth generation (5G)
wireless, such as mm-wave, massive
MIMO, and low-latency communications. To go beyond this vision, we
explore the ideas of directional mesh
networks that can replace the wireless
infrastructure, relaying for increased
capacity and connectivity for billions
of Internet of Things devices.

"Efficient Time-Interleaved
Analog-to-Digital Converters"
While time interleaving has been
introduced as a method to overcome
inherent speed limitation in earlier
CMOS technologies, today it is primarily being used to enable higher
energy efficiency of high-data rate
ADCs. High efficiency is obtained by
designing efficient ADCs themselves
and by having a low interleaving
overhead. This talk presents design
techniques for minimizing the overhead of the calibration of timing
and bandwidth mismatches necessary for minimizing the interleaving
artifacts. Design examples of interleaved pipeline and SAR converters
will be presented.
-Seng-Pan U (Ben)
SSCS-Macau Founding Chapter Chair

Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Winter 2016