IEEE Solid-State Circuits Magazine - Winter 2016 - 82
based on III-nitride heterojunctions
can be expected to achieve ON/OFF
ratios of 106 or more, with switching
slopes well below 60 mV/decade, ONcurrent densities approaching 100 μA/
μm, and energy delay products as low
as 67 aJ-ps/μm.
"Transistor Switches Using Active
Piezoelectric Gate Barriers"
by R.K. Jana, A. Ajoy, G. Snider, and D.
Jena (this article contains multimedia)
This paper explores the consequences of introducing a piezoelectric
gate barrier in a normal field-effect
transistor. Because of the positive
feedback of strain and piezoelectric
charge, internal charge amplification
occurs in such an electromechanical capacitor, resulting in a negative
capacitance. The first consequence
of this amplification is a boost in the
ON-current of the transistor. As a
second consequence, employing the
Lagrangian method, we find that using
the negative capacitance of a highly
compliant piezoelectric barrier, one
can potentially reduce the SS of a transistor below the room-temperature
Boltzmann limit of 60 mV/decade.
However, this may come at the cost
of hysteretic behavior in the transfer
characteristics.
"Sub-kT/q Switching in Strong
Inversion in PbZr0. 52Ti0.48O3 Gated
Negative Capacitance FETs"
by S. Dasgupta, A. Rajashekhar, K.
Majumdar, N. Agrawai, A. Razavieh,
S. Troiier-McKinstry, and S. Datta
Hysteretic switching with a sub-kT/q
steep slope (13 mV/decade at room
temperature) is experimentally demonstrated in MOSFETs with PbZr0.52Ti0.48O3
as a ferroelectric (FE) gate insulator,
integrated on a silicon channel with a
nonperovskite high-k dielectric (HfO2)
as a buffer interlayer. The steep switching is independent of drain bias. For the
first time, sub-kT/q switching due to FE
negative capacitance is observed not at
low currents but in strong inversion
(I d ` 100 nA/nm) . Steep switching in
strong inversion provides an important
point of consistency with the predictions of the Landau-Devonshire theory
and the Landau-Khalatnikov equation.
82
w i n t e r 2 0 16
Benchmarking Methodology
and Analyses
"A Material Framework for
Beyond-CMOS Devices"
by K. Galatsis, C. Ahn, I. Krivorotov,
P. Kim, R. Lake, K.L. Wang, and J.P. Chang
(this article contains multimedia)
Beyond-CMOS device concepts are
greatly dependent on new functional
materials to provide inspiration and
innovation beyond the silicon status
quo. Here, we propose a material framework specifically for beyond-CMOS
devices. In doing so, material system
examples and data points presented
are taken from the Center on Functional
Accelerated Nanomaterials Engineering, the STARnet Center of Excellence.
"Benchmarking of Beyond-CMOS
Exploratory Devices for Logic
Integrated Circuits"
by D.E. Nikonov and I.A. Young (this
article contains multimedia)
A new benchmarking of beyondCMOS exploratory devices for logic integrated circuits is presented. It includes
new devices with FE, straintronic, and
orbitronic computational state variables. Standby power treatment and
memory circuits are included. The set
of circuits is extended to sequential
logic, including arithmetic logic units.
The conclusion that TFETs are the leading low-power option is reinforced. FE
transistors may present an attractive
option with faster switching delay. Magnetoelectric effects are more energy
efficient than spin transfer torque, but
the switching speed of magnetization is
a limitation. This paper enables a better focus on promising beyond-CMOS
exploratory devices.
Spintronic Devices and Interconnect
(Based on Magnetics and
Spin Physics)
"Interconnects for All-Spin Logic
Using Automotion of Domain Walls"
by S. Chang, S. Dutta, S. Manipatruni,
D.E. Nikonov, I.A. Young, and A. Naeemi
(this article contains multimedia)
In this paper, an interconnect
scheme based on the automotion of domain walls (DWs) for all-spin logic (ASL)
IEEE SOLID-STATE CIRCUITS MAGAZINE
is proposed. The proposed interconnect
is analyzed using a comprehensive numerical model including an equivalent
circuit for ASL operations, the 1-D Landau-Lifshitz-Gilbert equation for DW
creation, reflection, and disappearance
at the boundaries. Analytical expressions for DW transport along the wire
are also presented. From the model, it
is found that the reflection of the DW
can be eliminated using a material with
a high Gilbert damping coefficient at
the end, the energy dissipation can be
independent of the interconnect length,
and DW displacement and energy dissipation can be further improved using a
material with a low damping factor and
saturation magnetization. Furthermore,
the interconnect reliability is also studied by applying the thermal random
noise analysis on the dynamics of DWs,
and it is found that thermal fluctuations can have a significant impact on
the interconnect performance; thus, the
interconnect with a low Gilbert damping factor is desired to suppress the
thermal noise effects.
"Magnonic Holographic Memory:
From Proposal to Device"
by F. Gertz, A. Kozhevnikov, Y. Filimonov, D.E. Nikonov, and A. Khitun
(this article contains multimedia)
This work describes recent developments in magnonic holographic
memory devices exploiting spin
waves for information transfer. The
devices comprise a magnetic matrix
and spin wave-generating/detecting
elements placed on the edges of the
waveguides. The matrix consists of a
grid of magnetic waveguides connected via cross junctions. Magnetic memory elements are incorporated within
the junction while the read-in and
read-out is accomplished by the spin
waves propagating through the waveguides. Experimental data on spin
wave propagation through NiFe and
YIG magnetic crosses is presented.
The obtained experimental data show
prominent spin wave signal modulation (up to 20 dB for NiFe and 35
dB for YIG) by the external magnetic
field, where both the strength and the
direction of the magnetic field define
the transport between the cross arms.
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