IEEE Solid-State Circuits Magazine - Winter 2017 - 10

26

C1

76

28
φ 34 φ
14 φ

V1 ∝3C1

VIn

φ

62

-
+

16
24

12 C
22

30

18

38
φ

∝2C2
φ

60

44
Parasitic-Insensitive
Integrator

56

V01
70

78

C2
50

46

∝1C1

∝4C3

-
+

72 68
74

40 φ

φ

58

∝5C3

C

42
φ

C3
φ
82

84

φ 66

64

V0

∝1C1

32
36

80
φ

52

-
+

54

48

V2

Figure 2: the filter described by Gregorian in 1978, showing a parasitic-insensitive integrator.

C1
S1

S2

C2

Vin
S4

X

S3

-
A0
+

Vin

Vout

C2

(a)
C1
X

C1
C2 X

-
A
+ 0

Vout

-
+

(b)

A0

Vout

(c)

Figure 3: (a) A basic parasitic-insensitive integrator, (b) its operation in the sampling mode,
and (c) its operation in the integration mode.

Allstot et al. [3] and White et al. [4]. In
addition, Martin and Sedra describe
the circuit in Electronics Letters in
June 1979 [5]. It is interesting that
all these groups developed the same
concept at around the same time.

C1
Vin

S1 A C2 B

Cp1

S3

S4

x
Cp2

-
A0
+

Vout

Figure 4: the effect of parasitic capacitances on an integrator's operation.

10

w i n t e r 2 0 17

Basic Structure
Depicted in Figure 3(a), the parasiticinsensitive integrator controls the
sampling capacitor by four switches
and two nonoverlapping clocks.
First, S 1 and S 3 are on, allowing C 2
to charge to Vin [Figure 3(b)]. Next,
these switches turn off, and S 2 and
S 4 turn on, forcing the charge on C 2
to travel to C 1 [Figure 3(c)]. It is worth
noting that the snapshots of this circuit in the sampling and integration
modes look the same as those of the
topology in Figure 1(c), but the nonidealities have different effects.

IEEE SOLID-STATE CIRCUITS MAGAZINE

Suppose C 2 has a parasitic capacitance from each plate to ground. As
shown in Figure 4, the left-plate parasitic, C p1, does charge to Vin in the
sampling mode, but it is discharged
to ground by S 4 in the integration
mode. The right-plate parasitic, C p2,
is charged only slightly in the integration mode due to the finite gain
of the op amp. In other words, the
charge delivered to C 1 has no contribution from C p1 and very little
from C p2 . This point also applies
to the nonlinearities arising from
these parasitics.
The use of nonoverlapping clocks
for S 1, 3 and S 2, 4 in Figure 3(a) is necessary for avoiding the simultaneous
activation of 1) S 3 and S 4, which would
corrupt the value stored on C 2, and
2) S 1 and S 2, which would allow Vin
to momentarily charge C 1 through
C 2, reducing the integrator gain as
explained in the following.
The integrator of Figure 3(a) also
avoids cha nnel cha rge-injection
effects by proper sequencing of the
switch controls. Specifically, if S 3
turns off before S 1 does, then the
charge injected by S 1 is not deposited on C 2 (because S 2 is off) and
hence plays no role in the integration process. Switch S 2 does inject
charge onto C 1, but this charge is
independent of the input and introduces only a constant offset, an
effect unimportant in differential implementations.
The structure shown in Figure 3(a)
is a noninverting integrator. To see
this point, suppose Vin is constant and
equal to V0, placing on the right plate
of C 2 a charge amount equal to - C 2 V0
in the sampling mode. This charge
moves to the left plate of C 1 in the
integration mode, causing a change of
+ C 2 V0 /C 1 in Vout . An inverting integrator can be realized by changing the
switch controls so that S 1 and S 2 turn
on together, as do S 3 and S 4 [6].
As shown in Figure 5, in one mode,
Vin charges C 1 through C 2; in the
other mode, C 2 is reset. The circuit
resembles an inverting amplifier in
the first mode, but, in fact, it integrates because C 1 is not reset. [We
can now see why simultaneous turn



Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Winter 2017

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