Kiran Gunnam, Joan Marc Català Pérez, and Francisco Garcia-Herrero Algorithms and VLSI Architectures for Low-Density Parity-Check Codes Part 2-Efficient coding architectures T his article is the second of a two-part tutorial about low-density parity-check (LDPC) codes. (The first part appeared in the Fall 2016 issue.) Here, we describe the min-sum decoding algorithm and explain the very-largescale integration (VLSI) architectures for nonlayered and layered decoders and the techniques to reduce memory and logic requirements in their implementations, pointing out the advantages and disadvantages of each. The Min-Sum Algorithm The first LDPC decoding algorithm was based on the sum-product algorithm (SPA) [1], which applied sums and products in the check node to update messages. Due to its complexity and the required increase of hardware resources, some suboptimal solutions were proposed. The min-sum algorithm is a reduced complexity decoding algorithm that, compared to the SPA, simplifies operations in the check node [2]. The check-node algorithm can be computed in two phases. In the first phase of iteration l, the magnitudes of the messages are computed. These magnitudes represent the output messages' reliability. The Digital Object Identifier 10.1109/MSSC.2016.2622998 Date of publication: 23 January 2017 1943-0582/17©2017ieee IEEE SOLID-STATE CIRCUITS MAGAZINE w i n t e r 2 0 17 23