IEEE Spectrum January, 2014 - 61

top 10 tech

2014

Fun FAct: When it comes to memory manufacturing, consolidation is king.
Today only three major DRAM manufacturers remain: Micron, Samsung, and SK Hynix
will allow the memory
manufacturers to take
what's essentially a right
turn around Moore's Law:
They'll pack more bits
together not by shrinking
features but by layering cells.
The change in architecture
is expected to drive down
the cost per bit and relax
lithographic printing
requirements. Indeed,
Samsung's new 3-D cells
are likely made with
a 30- to 40-nanometer
process, a few generations
behind the current, 20-nm
class, says Dee Robinson,
a senior analyst at IHS in
El Segundo, Calif. With bigger
cells and more electrons,
Robinson says, "it's actually
a better performing chip."
She adds that it's still unclear
how quickly the cost of the
new technology will decline
to match that of traditional
2-D flash. But IHS estimates
that 3-D flash will make up
more than half of the NAND
market by 2017.
The move carries some
risk. "It involves technologies
that have never been put
into production before,"
says analyst Jim Handy of
Objective Analysis in Los
Gatos, Calif. While some flash
manufacturers are moving
to 3-D, others, such as Intel,
SanDisk, and Toshiba, are
expected to stick with planar
NAND for the moment, by
taking advantage of new
insulating materials. But they
will inevitably be forced to
switch to 3-D, Handy says.
A second 3-D technology-
the Hybrid Memory Cube,
illustration by

James Provost

3-D nAnD

Via electrode
contacts

Channels

NAND cell string

HybriD
MeMory cube
DRAM layer

Logic
Substrate
TSVs
two takes on 3-D memory: To boost density and alleviate scaling
issues, 3‑D NAND [top] stands the traditional planar channel, and
the line of memory cells arranged along it, straight up. A second 3‑D
technology, the Hybrid Memory Cube [bottom], will stack DRAM and add
a layer of logic to boost speed.

or HMC-will also be ramping
up in 2014. This effort
focuses not on storage but
on the computer's memory
workhorse: dynamic RAM.
The HMC won't be
any denser, smaller, or
cheaper than an ordinary
DRAM chip-it'll be faster.
It's designed to surmount
the "memory wall," a
communications bottleneck
that has developed between
multicore CPUs and memory,
says Mike Black, a technology

strategist at Micron. "The
latest generations of highperformance CPUs are not
capable of getting access to
enough memory bandwidth,"
Black says.
Micron developed the
HMC in collaboration with
SK Hynix and Samsung
as well as more than
100 other semiconductor
firms, research institutions,
and potential customers.
Their aim was to change
the way systems handle
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DRAM signals. Instead of
forcing DRAM chips to drive
communications straight to a
processor, the HMC off-loads
most of that responsibility
to a high-speed logic chip.
DRAM dies are stacked
atop this logic layer and are
connected using thousands
of copper wires called
through-silicon vias (TSVs).
These vias allow the DRAM
chip broad access to its
bus; the logic layer cuts the
number of connections that
information must traverse
on its way to the CPU. "This is
the first commercial memory
product offering [TSVs]
as a standard part of the
construction," Black says.
Micron announced in
September that it had
begun shipping the first
samples of its 2-GB memory
cube. They're expected
to be produced at volume
later this year, along with
a 4-GB version. A single
cube can offer 160 gigabytes
per second of bandwidth,
Micron says, compared with
about 12 GB/s for current
DRAM and 20 for the next
generation, DDR4.
The HMC is quite fast, says
Handy of Objective Analysis,
but its success will hinge on
finding a sufficiently large
market to drive down costs.
A large player such as Intel
could sway the technology's
fate. But "so far," he says,
"Intel's been playing it close
to the vest."
-R achel couRtl a nd
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Table of Contents for the Digital Edition of IEEE Spectrum January, 2014
