IEEE Spectrum February, 2015 - 16

designing circuits that could vaporize metallic tubes, leaving only the
semiconducting ones behind. Now
they've refined the fabrication process to boost the density of carbon
nanotubes while preserving the
level of uniformity.
Their fabrication process begins
with quartz, on which the carbon
nanotubes are grown. A layer of
gold is deposited on top and then
peeled away with thermal tape, taking the nanotubes with them. The
nanotubes can then be transferred
to the target surface, where the
thermal tape is eased off and the
gold chemically removed, leaving
an array of parallel carbon nanotubes on the surface.
One t ra nsfer y ields a rou nd
eight nanotubes per micrometer,
as measured perpendicular to the
direction that current would flow
across the devices. But in this latest work, the team showed they
could repeat this deposition process more than a dozen times by
laying down a gluelike polymer
before each successive deposition
of carbon nanotubes. The polymer
prevented the carbon nanotubes
from sticking to one another and
becoming a spaghetti-like mess
when exposed to the liquid used to
etch away the gold. It also helped
smooth the surface for the next
layer of nanotubes.
With this approach, the team
was able to make transistors with
an average density of 100 carbon
nanotubes per micrometer, giving
a current density of up to 122 microamperes per micrometer.
This is neither the highest density of carbon nanotubes nor the
highest current density that's been
achieved. In 2013, a team based at
IBM's Thomas J. Watson Research
Center, in Yorktown Heights, N.Y.,
reported that a suspension of carbon nanotubes in oil could be used
to produce more than 500 carbon
nanotubes per micrometer and similar current densities.
But i n t he I BM ex per i ment
there were metallic carbon nanotubes in the mix, which conduct
current even when a transistor
is supposed to be off. This may
have contributed to a fairly low
ratio of on-current to off-current,
which, in the shortest IBM transistors, maxed out at around 600:1,
Shulaker estimates. The Stanford
team's ratio is around 6,000, an
indicator that only a small amount
of current is leaking through the
devices when they're supposed to

fEb 2015

nORTh aMERICan

be off. (Designers typically aim for
an on/off ratio of about 10,000 for
the CMOS devices used in smartphone and computer processors.)
To prove the approach's compatibility with silicon, the Stanford team
used the multiple-transfer strategy
to create a "monolithic" 3-D integrated circuit. A monolithic IC is
made in one fell swoop on a single
silicon substrate by building layers of
devices one on top of the other, with
dense metal wiring connecting them.
The team built a crossbar switch-
a circuit that can be used to connect
different inputs and outputs-out
of a layer of silicon, two layers of
resistive RAM, and then a layer of
carbon nanotube transistors. They
were able to build the stack of circuits without raising temperatures
above 400 °C, which could damage
the transistors.
"These guys are masters of stacking," says Sung Kyu Lim, who works
on monolithic 3-D design at Georgia Tech. Although researchers at
CEA-Leti, in France, have stacked
logic on top of logic, Lim says this is
the first demonstration he's seen of
memory and logic stacked together
in a monolithic fashion: "They're
the first one demonstrating that
this is possible," he says. The combination of logic and memory could
dramatically reduce the time and
energy needed to move information inside a computer.
But bringing carbon nanotube
ICs into mass production could
still be a ways off, Lim notes. The
current-carrying channels in the
Stanford team's carbon nanotube
transistors are 400 nanometers
long, about 10 times the size of stateof-the-art devices. "You want the
devices to be smaller and the circuits to be larger," Lim says.
The next step is indeed building speedier circuits with shorterchannel transistors, Wong says.
And it should be possible; previous work at IBM has shown carbon
nanotube transistors with channel lengths smaller than 10 nm.
But Wong says there are hurdles
that must still be overcome on
the road to high- performance
circuits. First on his list are the
metal contacts that connect to
the nanotubes, which, like the
contacts in other devices, balloon
in resistance as they get smaller.
Still, he has high hopes: "Having
a technology that can compete
with silicon in an academic setting
would be tremendously exciting."
-r achel cou rtl a nd

SPECTRUM.IEEE.ORG

AvertinG
spACe doom
orbital debris could become a serious
concern. How will we deal with it?
We are closer than ever to witnessing
the "Kessler syndrome," a scenario
proposed in 1978 by NASA scientist
Donald Kessler in which the high density of objects and debris in low Earth orbit creates
a cascade of collisions that renders space travel and
satellite use impossible for decades. However, how
close we really are is a matter of debate.
The United States Space Surveillance Network,
operated by the Air Force, estimates there are
more than 500,000 pieces of debris larger than
1 centimeter orbiting Earth today, including 21,000
pieces larger than 10 cm that are actively tracked.
And that's ignoring the millions of smaller bits that
are also up there. The average speed at which space
junk would collide with a satellite is approximately
10 kilometers per second, meaning collisions with
debris as small as 0.2 millimeters can still do damage.
Next month, engineers will gather at the 2015 IEEE
Aerospace Conference, in Big Sky, Mont., to figure
out what the real dangers are and what, if anything,

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Table of Contents for the Digital Edition of IEEE Spectrum February, 2015