IEEE Spectrum - North American - March 2014 - 19

SecOnd STOry

Transistor contact

This monolithic manufacturing scheme,
developed by CEA-Leti, builds two tiers of
circuitry using silicon from two separate
wafers. (Some steps are not shown.)

Multilayer
transistor contact

New wafer
Gate

Insulator

Channel
Source

Drain

Cea-LeTI

The firST lAyer of transistors-and the metal wires
used to connect them-
is built on a silicon wafer.

The circUiTry is coated
with a layer of oxide to serve
as electrical insulation.

A new wAfer containing
a layer of oxide sandwiched
between two layers of silicon,
one thick and one thin, is
bonded upside down on the
first layer.

The bUlk of the wafer
and oxide are removed,
and a second layer of
circuitry is built on top of
the remaining silicon.

to create a second layer of transistors could
search, Vinet says, Leti worked closely with
destroy crucial components in the first, in- manufacturing partner STMicroelectronics.
cluding salicide, a metal-silicon alloy used "There is no major roadblock to the transfer
of this technology to foundries," she says.
to help carry signals in and out of devices.
Now, research into lower-temperature pro- "I feel very confident when I say that."
Leti isn't the only group exploring monocesses is picking up. Leti has developed one
scheme [see illustration, "Second Story"] lithic fabrication. At the same meeting, for
that bonds a second silicon wafer on top of
example, a team led by Jia-Min Shieh of
the first tier of circuitry. All but a thin silicon
the National Nano Device Laboratories, in
layer on this second wafer is stripped away. Hsinchu, Taiwan, presented two-tier circuits
A second layer of transistors is built using a
made by growing silicon atop a layer of tranprocess called solid-phase epitaxy, in which
sistors instead of adding a second silicon
a mixture of dopant atoms and amorphous wafer. The Taiwan team's low-temperature
silicon is laid down. The mix is then heated
process isn't sufficient to create perfect
to just 600 °C, giving the silicon enough en- single-crystal silicon, so the process might
ergy to crystallize. As a last step, connections
are made by etching holes down to the first
layer and filling them with copper.
This approach has been used to create
basic circuits, such as inverters, that span
two chip layers. And last year, Leti reported
that devices fabricated with this process
perform as well as those made at higher
temperatures. The work is now getting
the attention of chipmakers. In December
2013, during the IEEE International Electron Devices Meeting in Washington, D.C.,
Leti announced that it had entered into an
TwO-STOry circUiT: Multistory circuits
agreement with mobile chip powerhouse
could let chipmakers increase the density
Qualcomm to evaluate the technology for
of devices on a chip without having to
mass production. In the process of this reshrink transistors.

hOleS Are eTched down
through the stack and filled
with metal. The resulting
interconnect can wire two
layers together [left] or access
each layer individually [right].

be suitable only for creating memory, which
tends to be more tolerant of crystal defects,
Shieh says.
When it comes to memory, monolithic
3-D fabrication already seems to be making
inroads in industry. In August, Samsung announced it had begun production on NAND
flash with memory cells arranged along
dense vertical lines, and other companies
have similar plans. But details are scant on
the particulars of the manufacturing process.
"Memory looks like it's already commercialized. Logic has a long way to go," says
Sung Kyu Lim of Georgia Tech. Lim, who is
working on monolithic 3-D circuit design,
says there are open questions that can be
resolved only when research progresses
from simple components to full-size chips.
Manufacturing imperfections and variations
could lower yield and make monolithic 3-D
chips more expensive. He adds that transistors made at lower temperatures may not
perform as well as their high-temperature
brethren, a shortcoming that would necessitate larger and thus less dense transistors
in the upper stages of designs. Still, he says,
as chipmakers bump up against fundamental physical limits, they may find themselves
short on options. In the future, he says, "the
only way to go to add more devices will
be vertical." -r achel courtl a nd

nEwS

SPECTRUM.IEEE.ORG

nORTh aMERICan

MaR 2014

http://SPECTRUM.IEEE.ORG

Table of Contents for the Digital Edition of IEEE Spectrum - North American - March 2014