IEEE Spectrum May, 2013 - 16

Now two researchers working in France,
Guilhem Larrieu of the Laboratory for
Analysis and Architecture of Systems, in
Toulouse, and Xiang-Lei Han of the Institute for Electronics, Microelectronics, and
Nanotechnology, in Lille, report the creation of a nanowire transistor that could
be scaled down to do the job. It consists of
an array of 225 doped-silicon nanowires,
each 30 nm wide and 200 nm tall, vertically linking the two platinum contact
planes that form the source and drain of
the transistor. Besides their narrowness,
what's new is the gate: A single 14-nm-thick
chromium layer surrounds each nanowire
midway up its length.
That thickness, the gate length, is the key.
"The advantage of an all-around gate allows
the creation of shorter gates, without loss
of control on the current through the channel," explains Larrieu. "We demonstrated
the first vertical nanowire transistor with
such a short gate." An all-around gate will be
a must if gate lengths are to get smaller than
10 nm, he says. In that scheme, "the size of
the gate depends only on the thickness of

the deposited layer; there is no complicated
expected to provide the best gate control
lithography involved," he adds.
for very short channels, she says.
The nanowires were of an unusual conDavide Sacchetto, a researcher at the
École Polytechnique Fédérale de Lausanne,
struction. Unlike with most vertical nanowire
transistor prototypes, in which the nano- agrees: "The fabrication of the gate is interwires are grown upward from a substrate, esting, and you get a small gate length." Howthe French duo created their nanowires by ever, the advantage is lost if the nanowires
starting out with a block of doped silicon and
are too long-200 nm in this case-and the
then etching away material to leave nano- channel is only a small part of the total
pillars. In between the pillars, they deposited
length of the nanowire, he says. "Even a
an insulating layer to about half the pillars' difference of 5 nm would make a huge difheight. Then they deposited the 14 nm of
ference in the drain current."
chromium and filled the remaining space
According to Judy Hoyt, a researcher at
with another insulating layer. "We tried to
the Microsystems Technology Laboratories
make the process completely compatible
at MIT, gate-all-around technology is now
with current technology used in electronics. under study at a number of university labs
No new machines will have to be invented," worldwide. But as the nanowire transissays Larrieu. The researchers have plans to
tors are more complex than the FinFETs,
try to go below 10-nm gate length, and also will this effort allow Moore's Law to live
to use indium gallium arsenide nanowires
longer and fit even more transistors on a
because of the better electron mobility.
chip? "The jury is still out," says Hoyt. It
Kelin Kuhn, director of advanced device
depends on what the fabrication process
technology at Intel's Hillsboro, Ore., loca- and the structure will be, she says. "You
really have to get the physics right, and
tion, agrees that all-around gate structures
have some key advantages. Of all the CMOS- that is what all these efforts are based on."
style advanced devices, they're generally -a lex a nder hellem a nS

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May 2013

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BlaDDer-Bot Vanderbilt University engineers have invented a 5.5-millimeter-wide robot
designed to snake through the urethra to find and remove bladder tumors.

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Table of Contents for the Digital Edition of IEEE Spectrum May, 2013