IEEE Spectrum July, 2012 - 36

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arithmetic logic unit, the core logic circuitry at the heart of a
CPU, can easily contain hundreds of transistors and require
the analysis of trillions of combinations, each of which would
take a few minutes to calculate. Today's microprocessors
easily contain more than a billion transistors, resulting in an
effectively infinite number of combinations.
It turns out this exercise in combinatorics is more difficult for
some sorts of circuits than for others. For a basic logic gate, it's
actually fairly easy to at least predict the worst-case scenario of a
circuit. That's because the pFETs and nFETs in logic are only on
for a fraction of the time and never at the same time, making the
calculations much easier. But that isn't the case for the flip-flop
circuitry that's interleaved throughout a processor and used to
clock computations or for static RAM (SRAM) memory cells,
which now easily take up half the space on a smartphone chip.

wIdEnIng varIabILITy: the range of threshold voltages-
those needed to turn a transistor on-is widening as circuit
feature sizes shrink from 28 nanometers [green line] to 20 nm
[blue] and 14 nm [red]. As feature sizes get smaller, an increasing
fraction of transistors are made with threshold voltages at or
below zero, which means they no longer operate as switches.

First, though, let's take a look at the long-

standing strategy for tackling global variations. This
approach relies on models that outline extreme process
deviations-all the possible manufacturing scenarios for a
chip. Fabs and foundries tend to measure these parameters
on the production floor, by deliberately fabricating test chips
that are way out of spec in one direction or another. Engineers
then measure the electrical properties of the transistors on
these extreme chips. The resulting set of specs-which can be
represented using a square-is called a corner model.
The four corners of the model can help engineers anticipate how any circuit will behave. In one corner, both the positively and negatively doped field-effect transistors-pFETs and
nFETs, respectively-are fast. In the other three corners you
find the three other pairings: slow pFETS with slow nFETS,
fast pFETs with slow nFETs, and slow pFETs with fast nFETs.
Chipmakers and designers assume there is an equal chance
that a circuit will fall into any one of these four corners.
This model breaks down, however, when circuits suffer
strongly from local process variation. With process variability,
every single nFET or pFET may operate either slower or faster
than average, and the performance of one device will be completely uncorrelated with that of its neighbor. For most circuits,
there will be far more than four possible behaviors, and not all
of them will be equally likely. Because the number of combinatorial possibilities effectively grows exponentially with the
number of devices in the circuit, the problem would challenge
even the largest computing clusters-called compute farms-
that chipmakers use to characterize their circuit libraries.
Consider the simplest digital circuit, an inverter, built
using one pFET and one nFET. A single inverter would have
four possible behaviors and thus a clear worst-case behavior.
But combine two inverters in an integrated circuit and you'll
either double or quadruple the number of possible behaviors,
depending on how they're connected. The problem only gets
worse as you scale up. One step up from the inverter in complexity is the NAND gate, which contains two nFETs and two
pFETS and could take on 16 possible behaviors. A very simple
36

NA * iEEE SpEctrum * july 2012

eVen iF it were easy to figure out the worst-case scenario, we wouldn't be able to estimate how many such bad
chips we'll generally get in a batch. We can't even say whether
the chance of producing such a chip is one in a billion or just
one in a thousand. Yet you need some guidelines of this sort
to push the performance of your design as far as possible
without reducing the yield to uneconomic levels. In the chipmaking business, there is no more unforgiving measurement
than yield. It is what determines your break-even point, the
point below which you might as well close shop.
Fortunately, we can get guidelines for yield even before
the manufacturing process starts, something that was never
really possible with the corner model. Since around 2005,
a new class of circuit analysis tools based on statistics has
let engineers anticipate an unacceptably low yield and introduce modifications that will make the final manufactured IC
more robust, such as increasing the size of the transistors that
cause most of the delay and variation in a circuit.
So far, most of the effort in the digital realm has focused on
revamping one of the core tools for logic design: static timing
analysis. STA predicts the maximum operating frequency of
an IC, which is determined by the longest time it takes a signal
to propagate through logic gates. Nowadays, however, STA
doesn't work so well, since each chip will have its own delay,
and some will be able to run quite a bit faster than others.
A statistical version of the STA tools, called SSTA, can be
used to calculate not only the theoretical operating frequency
of a design but also the probability that the manufactured
version will in fact operate correctly at that frequency. This
turns out to be fairly easy to calculate, because the delay in
logic is almost always a linear operation and the computational power needed to handle the analysis is not excessive.
But SSTA is only as good as the data you supply to it. The
tools need timing information based on statistics describing
basic transistor variation. You could create such statistics by
simply summing the effect of each source of variation on the
behavior of a circuit, but the problem with such "sensitivity
analysis" is that most sources of variation can't be considered independently. If, for instance, a transistor's channel
is longer than expected, then more voltage will be needed
to turn the transistor on. As a result, voltage and channel
length are linked. If you add the variation from each source
separately, you'll effectively be counting the same effect multiple times, overestimating how much local process variation
affects circuit timing.
spectrum.ieee.org

data: asen asenov

Threshold voltage (volts)

http://spectrum.ieee.org

Table of Contents for the Digital Edition of IEEE Spectrum July, 2012