IEEE Spectrum July, 2012 - 37

imec

the chip-to-chip variation in signal-processing speed. It turned
The case is particularly bad for clocking circuitry: My
out to be closer to 70 percent. This variation has a big impact:
colleagues and I calculated that sensitivity analysis overesIf chipmakers use an SSTA model of the SoC that doesn't account
timates timing delay, as well as two key measures of flip-flop
for such variation in memory, they can overestimate the maxiperformance, by a factor of two to three. Chipmakers who rely
mum operating frequency of a chip by as much as 10 percent.
on this kind of analysis will end up overestimating how much
Such a mistake raises the probability of creating bad chips.
they must widen transistors to increase current flow and thus
The Reality project has also helped identify what it would
the circuit speed. When the resulting processors are made,
take to model the variation in an entire SoC. But although my
they'll run 10 to 20 percent faster than expected, but they'll
team at Imec has transferred our memory tools for analyzalso carry-and leak-more current than they should. For
ing SRAM to a number of partners, including memory maker
flip-flops, which are very active, switching every single clock
Samsung, these tools don't work by themselves. They require
cycle, the design choice will result in a lot of wasted power.
a larger modeling framework capable of accommodating staAnother technique is CPU-intensive Monte Carlo analytistical design, something that few commercial packages can
sis. This approach uses loops, each of which selects values at
do and none can do for an entire SoC. Memories can account
random for basic transistor properties and "injects" them into
for up to half the maximum timing delay between input and
a transistor model, thus simulating the impact of local prooutput on such a chip, which means that right now we're misscess variations. Once this is done, an electrical simulation of
ing half of the problem and thus half of the solution. As it now
the circuit is performed. The process is repeated hundreds or
stands, it's not clear whether such chip-level analysis tools will
thousands of times, with different random values every time.
emerge by 2026, the most distant point now specified in the
As you might imagine, the problem with this approach is the
industry's road map. Chipmakers may
computer time it consumes. If a logic
simply opt to squeeze by with existing
library is composed of, say, 1000 buildstatistical tools for logic.
ing blocks or logic gates and every block
One project that's looking beyond
takes 3 seconds on average to simulate,
the end of the current road map is
a Monte Carlo loop of 1000 iterations
called Terascale Reliable Adaptive
would blow up the characterization
Memor y Systems (TR AMS). The
time from the single hour needed to
€3.5 million effort, backed in part by
simulate a corner in traditional corner
the EU, aims to study the possible
analysis on a CPU to more than a month.
effects of variability on some of the
Memory also turns out to be esperOugh gOIng: these uneven rows of
switching architectures that might
cially difficult to simulate. Statistical
exposed photoresist, created using extreme
replace the traditional CMOS tranmodels tend to use a single SRAM bit to
ultraviolet light, will become 30-nanometersistor. These include 3-D transistors
model the behavior of the entire memlong transistor gates.
built on an insulating layer, devices
ory chip. But memory is only as fast as
made with compound semiconductors,
its slowest bit. Bits are read in groups-
and logic based on carbon nanotubes.
or bytes-and each group must wait for
Some of these devices may be able to tune their electrical
all its bits to return values. Because a memory chip is basically
properties without dopants, and TRAMS will help determine
composed of a grab bag of bits with different properties, it is all
whether this simplification will ease the variability problem
too likely that at least one of the billion or so bits will have an
or other sources of variation will crop up to take its place.
extremely long delay time. Although there are tricks that can
Most design efforts aim at avoiding variability. One notahelp make Monte Carlo simulations speedier, statistical tools
ble exception is the multi-institution, U.S. National Science
that can optimize memory are still lacking.
Foundation-funded Variability Expedition, which aims to
develop ways to adapt to the problem. A promising way to
do this is with circuit components that use proactive, on-chip
My colleagues and i began to get a taste of how far
hardware and software to monitor and dynamically adapt
we have to go-particularly in modeling memory-in 2008,
to imperfect chips [see "CPU, Heal Thyself," ieee spectrum,
when we began Reality, a €4.5 million, six-institution
August 2009].
research project funded by the European Union. We aimed
If all goes well, these research efforts will help identify the
to create something completely new: a variability-sensitive,
best way to handle variability. But it is clear that designers
fully statistical model of a system-on-a-chip (SoC), the comcan't do the job alone. New devices and circuits will likely be
bination of memory and processor that forms the CPUs of
crucial to reducing the impact of variability. And chipmakmost tablet computers and smartphones.
ers may also get some relief from the problem in a few years'
To accomplish this task, we combined transistor data protime, when they switch their manufacturing process from
vided by project member STMicroelectronics with statistical
300-millimeter-wide wafers to 450-mm versions. Fabs will
tools developed at the University of Glasgow and at Imec, in
then be able to produce more chips per hour and will thereBelgium. This allowed us to model a representative subset of
fore lose less money, proportionally, to out-of-spec chips.
chip designer ARM Holdings' library of circuit building blocks
In one form or another, variability will continue to plague
and one of ARM's cores. Along the way, we devised a trick
us as we approach atom-scale switches. All we can do is
for quickly modeling memory variations in the ARM SoC by
make sure we have the tools we need to meet it head-on. o
assigning random timing and power properties to components
on the chip. The project produced more than a few surprises.
post your comments online at http://spectrum.ieee.org/
Our back-of-the-envelope calculations had led us to expect
variability0712
that the SRAM on the chip would cause only 10 to 20 percent of
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Table of Contents for the Digital Edition of IEEE Spectrum July, 2012