IEEE Spectrum July, 2013 - 38

material is flush with the surrounding sili- Hit the sweet spot-enough
silicon to boost mobility but
con surface, most of the defects have ended
at one of the trench's sidewalls [see illustra- not so much that it degrades
crystal quality-and germation, "Where the Defects Stop"].
Matty Caymax, a chemist who specializes
nium hole mobility could in
in postsilicon device fabrication at Imec, set theory jump by as much as
out with his colleagues to see if they could
a factor of six.
make this approach fast, robust, and reliable
enough to work in silicon fabs. Trenches
in 2008, iMec's engineers
themselves aren't new to the semiconductor reported a record current
industry: For 15 years, fabs have etched away for a germanium FET with a
silicon and then refilled the trenches with
65-nm gate length, a dimensilicon dioxide. Such "shallow trench iso- sion that was a few years belation" creates stretches of insulating sub- hind the state of the art for
silicon. But then progress
strate between transistors so they can be
packed closer together with minimal elec- ground to a halt. Part of the
delay came as the team transitrical interference.
Because silicon dioxide is noncrystalline, tioned from a 200-millimeter
it can be packed into a trench without re- wafer line to a 300-mm line.
But they also found they had
gard to where each individual atom ends
to tackle an unexpected issue:
up. Filling troughs with materials that have
a high charge-carrier mobility is another excess leakage.
There seemed to be too
matter. To work properly, they must form
high-quality crystals, even though the spac- much strain on the pure
germanium channel, so the
ing between their atoms is quite different
from that of the silicon they are grown on. engineers resumed work on
Germanium atoms are spaced, on average, silicon- germanium. They
built a ring oscillator that
0.566 nanometers apart, compared with
can switch 25 percent faster
0.543 nm for silicon atoms. InGaAs is even
than silicon equivalents at today's standard
worse, with a spacing of 0.59 nm. The basic
operating voltage, 1.1 volts, Caymax says.
mismatch easily results in stacking errors.
When Caymax and his group began work- At 0.9 V, the performance gap grows to
ing on alternate channels in 2002, they de- 40 percent. The group also demonstrated an
8-bit multiplier that can operate well at 0.6 V,
cided to focus on giving a speed boost to
pFETs. The pFET was a natural place to start. a level where silicon-based circuits struggle.
Now it seems that most of the kinks in
Holes don't move as fast through silicon as
electrons do. Without straining the crys- pure germanium have been worked out.
tal, a silicon pFET might carry only about "I cannot go into details, but we are now
a quarter as much current as an nFET can, in much better shape," says Caymax. In
Caymax says. Introducing a higher-mobility June, at the VLSI Technology symposium
in Kyoto, Japan, Caymax's colleague Jérome
material can address that imbalance.
Growing pure germanium on pure sili- Mitard presented new results for a pure
germanium design that's a stepping-stone
con was a big jump, so Imec first started
working with mixtures of silicon and ger- toward a germanium-based 3-D transistor,
manium, and then began experimenting which the team hopes to complete by the
end of this year. Their device can transmit
with growing a layer of pure germanium on
holes six times as fast as a silicon equivalent
top of the SiGe mix. The SiGe layer helped
ease the mismatch in atomic spacing, re- and can operate well at 0.5 V, which could
ducing the number of defects in the Ge. But mean significant energy savings.
The only drawback is the size: The channel
Caymax and his colleagues also realized
in the VLSI device is 200 nm wide. The tranthis approach gave them an extra knob to
turn. By fine-tuning the ratio of silicon and
sistors on today's chips boast channels that
germanium, the team could compress the
are about a tenth as wide, and even smaller
germanium channel that lies above it and
ones will be required for next-generation
slightly change the spacing between atoms. CMOS. But Caymax is optimistic. "There are
38

JUL 2013

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no obvious showstoppers to going further
down after this first run," he says, adding that
he and his colleagues have achieved "good
filling" with germanium in trenches that are
just 11 to 12 nm wide. If the team can halve
that, they will be in the ballpark needed for
the devices at the 7-nm node, about the point
at which industry watchers expect alternate
channel materials will be needed.
Building the nFET has turned out to be
trickier. The speediest materials for electrons are III-V compounds. Caymax's group
opted to make III-V transistors that were a
mix of two materials: a trench filled with
indium phosphide topped with a thin layer
of ultraspeedy InGaAs. Filling the bulk of the
trench with InP helps cut down on losses.
Current tends to leak across a transistor in
the deepest part of the transistor channel,
the area farthest from the gate. By making
the bulk of the trench out of InP, this avenue can be eliminated, because electrons
moving through InGaAs don't have enough
energy to jump into that material.
But filling a trench with InP is challenging. If the atoms are not ordered correctly,

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Table of Contents for the Digital Edition of IEEE Spectrum July, 2013