IEEE Spectrum November, 2013 - 12

wire in the INUMAC magnet is
made from niobium-titanium,
a common superconductor
alloy. But it will experience
some uncommon conditions
as part of INUMAC. To reach
the required field strength, the
electromagnet must be able to
carry 1500 amperes at 12 T and
be cooled by superfluid liquid
helium to 1.8 kelvins. That requires specialized manufacturing and precise control of the
dimensions of the wire, allowing
it to be coiled so the cables are
aligned to within a few micrometers of precision. "We are
pushing the superconducting
material niobium-titanium very
close to its limits," Védrine says.
Another material, niobiumtin, can produce magnetic
fields stronger than 20 T, but it
was passed over for the job because it's more expensive than
niobium-titanium and very brittle, making it difficult to wind.
Ultimately, Luvata produced
170 km of wire for the main superconducting coil. The company made another 58 km for
two secondary coils, which will
produce an opposing magnetic
field to shield the area outside
the machine from stray magnetic fields.
Instead of winding the wire
into one long coil, as is standard
in systems with lower fields,

The electromagnet must
be able to
carry 1500
amperes
at 12 teslas
while cooled
to 1.8 kelvins

nOV 2013

nORTh aMERICan

engineers are using a "double
pancake" design, in which the
wire is coiled into two reels that
are spliced together, one on top
of the other. The whole magnet will consist of 170 of these
double pancakes connected in
series. Védrine explains that
this reduces the chances for
error: Making a mistake in the
winding phase using a single
helical coil could ruin the whole
magnet. However, a miswound
pancake can simply be swapped
out for a new one. The design
provides space for the liquid
helium bath to reach all of the
coil and keep the temperature
low, and it also allows engineers
to place the best- performing
coils at the center of the system,
which improves the precision of
the magnetic field.
The inner diameter of the
magnet will be 90 centimeters,
wide enough for a human body.
Patients getting scanned will lie
entirely inside the machine, but
the region where the field is precise enough to get maximum
resolution will be only 22 cm
long. "The very good field region is only in the middle of the
magnet," Védrine says. While
patients could be situated so
that other body parts would fit
inside that region, "first we are
concentrating on the brain," he
says. It would take an even more
massive machine to enlarge the
high-resolution area.
Védrine expects to deliver
the fully assembled magnet by
September of next year. Other
parts of the imaging system will
then be added in and around
the magnet, followed by about
three months of testing. "Probably we'll have the first images by the beginning of 2015,"
he says. -neil savage

SPECTRUM.IEEE.ORG

the cache
machines
Many-core processors need the
flexibility of software to use their
onboard memory best
a new process for managing the fast-access
memory inside a CPU has led to as much as
a twofold speedup and to energy-use reductions of up to 72 percent. According to its designers,
realizing such stunning gains requires a big shift in what
part of the computer controls this crucial memory:
Right now that control is hard-wired into the CPU's
circuitry, but the substantial speedup came when the
designers let the operating system handle things instead.
The CPU uses high-speed internal memory caches as
a kind of digital staging area. Caches are a CPU's workbench, whether they're holding onto instructions a
CPU may need soon or data it may need to crunch. And
from smartphones to servers, nearly every CPU today
manages the flow of bits in and out of its caches using
algorithms built into its own circuits.
But, say two MIT researchers, as computers and portable devices accumulate more and more memory and CPU
cores, it makes less and less sense to leave cache management entirely up to the CPU. Instead, they say, it might
be better to let the operating system share the burden.
In itself, this idea is not completely new. Some of
IBM's Cell processors, as well as Sony's PlayStation 3-
which runs on Cell technology-allow their applications
and OS kernels to fiddle with low-level CPU memory
management. What's new about the MIT technology,
called Jigsaw, is its middle-ground approach, which
enables software to configure some on-chip memory
caches but without requiring so much control that programming becomes a memory-management nightmare.
"If you go back six or seven years, you'll see that
everybody was complaining that they launched the
PlayStation 3 and nobody could program it well,"
says Daniel Sanchez, the assistant professor at MIT's
Computer Science and Artificial Intelligence Laboratory and one of the inventors of Jigsaw.
Today, CPU hardware typically controls all the onchip caches. So those caches must be designed to handle
every conceivable job, from pure floating-point number
crunching (which places a small burden on caches) to
intensive searches and queries of a computer's mem-

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Table of Contents for the Digital Edition of IEEE Spectrum November, 2013