IEEE Spectrum November, 2013 - 29

"It is quite a controversial move," says William Arnold, chief scientist at ASML, the world's largest maker of semiconductor-fabrication
equipment. "The customers of the foundries, the people who are
making cellphone parts, are very skeptical of not being able to get
a shrink along with a performance improvement. They're pretty
vocal about saying that they're not happy about that."
ThE fOundriEs' laTEsT mOvE asidE, chips arE sTill mOrE Or lEss

When will the scaling stop? Today's patterning technology, which
relies on 193-nm laser light, is becoming an ever more costly challenge, and its natural successor, shorter-wavelength extreme
ultraviolet lithography, has been long delayed.
Kahng says chipmakers may face a more immediate struggle with
wiring in just a few years as they attempt to push chip density down
past the 10-nm generation. Each copper wire requires a sheath containing barrier material to prevent the metal from leaching into
surrounding material, as well as insulation to prevent it from interacting with neighboring wires. To perform effectively, this sheath
must be fairly thick. This thickness limits how closely wires can
be pushed together and forces the copper wires to shrink instead,
dramatically driving up the resistance and delays and drastically

doubling in density from node to node, says Andrew Kahng, a professor at the University of California, San Diego, and an expert on
high-performance chip design. But for Kahng, the steady progression of node names masks deeper problems. There is a difference,
he says, between "available density" (how closely you can pack
circuits and wires on a chip) and "realizable
density" (what you can actually put into a
competitive commercial product).
The sheer density and power levels on a
state-of-the-art chip have forced designers
to compensate by adding error-correction
circuitry, redundancy, read- and writeboosting circuitry for failing static RAM
cells, circuits to track and adapt to performance variations, and complicated memory
hierarchies to handle multicore architectures. The problem, Kahng says, is that
"all of those extra circuits add area." His
Planar
3-D
group has been scouring company specs
noDe: 20 nm // Manufacturer: Leading
noDe: 22 nm // Manufacturer: Intel
and deconstructing images of chips for
channel length: 30 nm // first Metal layer
foundries // channel length: 28 nm
first Metal layer Pitch: 64 nm
Pitch: 90 nm // fin wiDth: 8 nm
years, and they've come to an unsettling
conclusion: When you factor those circuits
in, chips are no longer twice as dense from
two transistors: Chipmakers are in the process of moving from traditional planar transistors
generation to generation. In fact, Kahng's
[left] to ones that pop out of plane [right]. Intel introduced these 3-D transistors in 2011, and they
are now shipping widely. The leading foundries, such as GlobalFoundries, Samsung, and Taiwan
analysis suggests, the density improveSemiconductor Manufacturing Co., are in the process of ramping up production of 20-nanometer
ment over the past three generations, from
planar transistors. They will make the switch to 3-D with the next generation.
2007 on, has been closer to 1.6 than 2. This
smaller density benefit means costlier chips,
and it also has an impact on performance
because signals must be driven over longer
distances. The shortfall is consistent enough, Kahng says, that it lowering performance. Although researchers are exploring alternacould be considered its own law.
tive materials, it's unclear, Kahng says, whether they will be ready
This might be a recoverable loss. So far, Kahng says, the chip
in time to keep up with Moore's Law's steady pace.
industry has made it a priority to keep up the pace of Moore's Law,
Many people in the industry, who have watched showstopper after
ensuring that manufacturers can continue to build and release new
showstopper crop up only to be bypassed by a new development,
product families while using a new process every 18 to 24 months. are reluctant to put a hard date on Moore's Law's demise. "Every
This means there hasn't been time to explore a number of design
generation, there are people who will say we're coming to the end
tricks that could be used to cut down on power or boost perfor- of the shrink," says ASML's Arnold, and in "every generation various
improvements do come about. I haven't seen the end of the road map."
mance. "When you're on that kind of schedule, you don't have
But for those keeping track of the road, those mile markers are
time to optimize things," he says. As the value of the simple shrink
decreases, he says, chipmakers should then be able to revisit their starting to get pretty blurry. n
designs and find chip-improving approaches they may have missed
or else left on the cutting-room floor.
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Table of Contents for the Digital Edition of IEEE Spectrum November, 2013