Antenna Systems & Technology - Fall 2016 - 8

FEATURE ARTICLE Figure 4. New antenna type with a single-layer antenna on a dielectric (green rectangle) that simulates its installation environment. The red dot indicates the chip position. Figure 6. Design 1, where the red dot indicates chip location. The antenna's dimensions are 94.4 x 23.7 mm, while the substrate overall is 162.2 x 91.5 x 2 mm. This antenna is unique in how its geometric constraints have Figure 5. Specifications used to synthesize RFID antenna four different substrates. The impedance used for been implemented. The outer dimensions of all other anten- across each band was to provide a conjugate-match to a chip with nas in the library are directly constrained by the user in the 16 - j148 Ω impedance [4]. geometry control. For this new type, the antenna's dimensions are set by the geometry control, but an additional set of antenna-specific parameters are used to set how far the dielectric extends beyond the antenna and how thick the substrate is. An example of this new antenna is shown in Figure 4. RFID Application Examples Two RFID antenna designs are presented. For both designs, as run within AntSyn, the specifications listed in Figure 5 were used. This set of specifications took only a few minutes to set up on the AntSyn web-based user interface and the run was executed using "medium quality," which means AntSyn was given a moderate computational budget for solving this problem. Edging, a WIPL-D EM solver-specific parameter, was used to increase the accuracy of the simulation at the expense of greater time required. A 2 mm substrate thickness was used, as in [4]. The resulting antenna design (Figure 6) had more than enough bandwidth to meet the target specification. However, the final design was scaled by +1.9 percent to maximize the performance in the target band of 902 - 928 MHz. The final size was well within the desired size envelope, at 94.4 mm by 23.7 mm. The resulting final input impedance of the antenna is shown in Figure 7 and the corresponding return loss (matching of conjugate antenna impedance to chip impedance) is given in Figure 8, including a wider frequency sweep using an external full-wave 3D simulator. Figure 7. Design 1 input impedance for the frequency range optimized in AntSyn. 8 Antenna Systems & Technology Fall 2016 Figure 8. Design 1 return loss over AntSyn optimized frequency range and also a wider frequency sweep using input impedance from external full-wave 3D simulation. www.AntennasOnline.com http://www.AntennasOnline.com

Table of Contents for the Digital Edition of Antenna Systems & Technology - Fall 2016