Medical Design Briefs - September 2021 - 16

TECHNOLOGY LEADERS Electronics
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AGND
FED
P DLY
5s RE DLY
START
PIN 1
ANALOG_ΙN
PIN 2
250 mV
2.5V
300mV
A
CMP1
300 mV
PIN 12
350mV
A
CMP2
350 mV
AGND
400mV
A
CMP3
400 mV
/12
500ms RE DLY
POR
CNT4/DLY4
DFF 6
2-L2
Very High Glucose LED
PIN 18
LDO0
PIN 11
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500ms RE DLY
POR
CNT3/DLY3
DFF 5
High Glucose LED
PIN 10
AGND
LDO1
PIN 13
/12
500ms RE DLY
POR
CNT2/DLY2
DFF 4
Normal Glucose LED
PIN 5
AGND
LDO2
PIN 14
POR
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2-LO
250mV
A
CMPO
/12
NETO
CNTO/DLY0
Very Low Glucose LRED
PIN 3
5V_IN
2.1V
500ms RE DLY
POR
CNT1/DLY1
DFF 3
PIN 15
Low Glucose LED
PIN 4
AGND
LDO3
PIN 16
ΙNV
FILTER0
nRESET
VDD
POR
OSCO
Fig. 3 - GreenPAK design.
Time (Seconds)
START
(ACMP0 PWR_ON)
Delayed ACMP0 output
(ACMP1 PWR_ON)
Delayed ACMP1 output
(ACMP2 PWR_ON)
Delayed ACMP2 output
(ACMP3 PWR_ON)
Delayed ACMP3 OUTPUT
5s DLY OUTPUT
Pin3
(Very Low Glucose LED)
Pin4
(Low Glucose LED)
Pin5
(Normal Glucose LED)
Pin10
(High Glucose LED)
Pin18
(Very High Glucose LED)
nRESET
(This section not to scale)
Fig. 4 - System signals when 300 mV < ANALOG_IN <350 mV.
ANALOG_IN signal received at Pin2 (see
Figure 3). This design has five possible
glucose levels, and each level corresponds
to a particular voltage range. Table 1 gives
Sr. No
1.
2.
3.
4.
5.
Analog Voltage
Range (mV)
0 ≤ V < 250
250 ≤ V < 300
300 ≤ V < 350
350 ≤ V < 400
V ≥ 400
the analog voltage ranges for each of the
glucose levels.
To prevent false readings, several 500
ms delay blocks are included between
Glucose Level
Very Low
Low
Normal
High
Very High
Table 1. Analog comparator outputs for different glucose levels.
16
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Medical Design Briefs, September 2021
µ
Glucose Level in
mmol/L
0 to 4
4 to 5
5 to 6
6 to 7.5
above 7.5
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10
the ACMPs and the rest of the circuit.
These delays will help filter out any spurious
signals. The sensitivity of the glucometer
can be varied by varying the
delay time of these delay blocks.
Since the voltage received at ANALOG_IN
(Pin2) is the result of the current
flowing between the counter electrode
and the working electrode on the test
strip, the current will only last for a short
period of time and may disappear quickly.
To hold the voltages for a longer period,
this example used capacitor C1. However,
even with the capacitor, the voltage will dissipate,
causing all of the ACMPs to be
LOW. To save the ANALOG_IN voltage
value, four DFFs are used to store the analog
voltage range information at the output
of the four delay blocks.
To reduce power consumption, each
ACMP is only powered on once. The
ANALOG_IN voltage is high enough for
the next ACMP to be required. For
instance, if the ANALOG_IN voltage is
325 mV and the START input goes
HIGH, ACMP0 will be turned on immediately
so that it can determine whether
ANALOG_IN is greater than 250 mV.
Since ANALOG_IN > 250 mV, after
500 ms, CNT1/DLY1 will go HIGH,
which will clock DFF3 and power on
ACMP1. ACMP1 will now check
whether ANALOG_IN is greater than
300 mV. Again, since it is greater than
300 mV, in 500 ms, the output of
CNT2/DLY2 goes HIGH, which clocks
DFF4 and powers on ACMP2. At this
point ANALOG_IN <350 mV, so ACMP2
will stay LOW, meaning that DFF5 and
DFF6 will both stay LOW.
Once 5 seconds has elapsed from the
time that the START signal went HIGH,
CNT0/DLY0 will go HIGH. This signal,
as well as the DFF outputs, are connected
to look-up tables (LUTs), either 2-bit
ACMP0 Output ACMP1 Output ACMP2 Output ACMP3 Output
Low
High
High
High
High
Low
Low
High
High
High
Low
Low
Low
High
High
Low
Low
Low
Low
High
NETO
NETO
NETO
NETO
nRESET
nRESET
nRESET
nRESET
AGND
VDD
3-bit
LUT11
3-bit
LUT5
3-bit
LUT4
2-bit
LUT1
POR
VDD
VDD
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NETO
NETO
È
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Medical Design Briefs - September 2021

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