Electrocardiogram Monitor Vdd Vda C1 100n 1 Meg 1 Meg ECG Out R3 2k2 + - ref Internal opamp 1 1 Meg 1 Meg R C2 100n VDD/2 Vref OSC 0 (2,048 kHz/12) + - Opamp 2 buffer Digital Rheostat Control Logic Interval P-R VDD/2 Vref + - Comparator P T P T + - Opamp 1 R SLG47004V R - R Interval R Q S Q systole diastole S Fig. 1 - Structure of ECG analog front-end. Fig. 2 - Typical ECG of healthy heart. OA1 +IN PIN 23 OPAMP 1 OA1 -IN PIN 24 OA0 +IN PIN 4 OPAMP0 OA0 -IN PIN 3 OA0 Out PIN 5 Rheostat middle point PIN 7 Comparator IN PIN 16 VDD/2 input PIN 12 power-up PIN 15 Power up OSCO Power up 12C SDA PIN 11 power-up RH1 RH1 A Rheostat1 B Logic RH1 B POR RHO B power-up A CMP0L RH0 RH0 A Logic RH0 B 12C SCL VDD 12C VDDA VDDA + V - AGND AGND RH0 A Rheostat 0 A PIN 6 RH1 B GND GND PIN 9 VDD VDD V2 + V - HD/B VREF 0A0 OPAMP INTERNAL ECG Out PIN 21 VDD/2 OUT PIN 20 RH1 A Rheostat1 A PIN 8 OA1 Out PIN 22 GND Fig. 3 - Design configuration of SLG47004. C6 100n 23 OA0 +IN to arm electrodes 4 0A0 +IN power up to 12C header 11 10 15 22 24 3 5 0AO out 0AO -IN 0A1 -IN 0A1 out Power up 12C SCL 12C SDA INT OA OUT CMP0 +IN RH1 A RH0 B VDD RH0 A VDDA RH1 B AGND GND 21 16 8 7 13 6 1 9 2 14 to microcontroller ADC Iinput C5 100n to microcontroller VDD R1 10R C1 10uf C2 100uf R2 10R CMP0 -IN SLG47004V vdd/2 ref 12 20 to leg electrode All electrical connections of the amplifier must be isolated from mains and from devices supplied from it. It is difficult to construct a power supply with a small amount of stray capacitance to mains. This article presents a batterypowered device that provides a simple solution for a low-cost and isolated power source with a minimum amount of stray capacitance. It details the integration of SLG47004, a fully programmable advanced analog system IC. The SLG47004 AnalogPAK can deliver only one instrumentation am - plifier, so this example uses AC filtering on the digital side. A simple DC reference point is used for a leg electrode without active interference cancelation. A simplified structural scheme of the top of the analog front-end is shown in Figure 1. A typical electric signal from a heart, picked up by the electrodes on the arms, is shown in Figure 2. The typical ECG waveform has five peaks called P-Q-R-S-T. These peaks correspond to the activity of different parts of the heart. The proposed design configuration is shown in Figure 3. It was created in the GreenPAK™ designer software. The complete design file can be found on the Dialog Semiconductor website.1 Electrical Schematic and Fig. 4 - Electrical schematic of analog front-end. 16 Cov www.medicaldesignbriefs.com ToC Configurations The electrical schematic of the analog front-end is shown in Figure 4. OpAmp0 and 1 use the same configuration, shown in Figure 5. The internal OpAmp configuration is shown in Figure 6, and the HD buffer shares the voltage reference with OpAmp0. In the current project, the internal Vref is disconnected from OpAmp0. The HD buffer and OpAmp0 Vref configurations are shown in Figure 7. Medical Design Briefs, March 2022 Bat 1 5V Bat1 10R 5v 10R R R4 I Meg C3 100n C4 100n R6 1Meg R7 2k2 R5 power-up power-up 1Meg 1Meg R3 power-up power-up R R C3 100uf POR Rheostat 2 Rheostat 1 100uf C4 POR power-uphttp://www.medicaldesignbriefs.com