Aerospace & Defense Technology - June 2024 - 16

Lasers & Optics
(a)
(b)
2
HTL (thin film based)
CQD layers
ETL (metal oxide NCs)
1
Example of the pixel stack
Figure 1. (a) SEM cross-section image of the CQD self-assembled film encapsulated by functional and protective
layers. (b) Schematic visualization of the p-i-n photodiode structure on the CMOS substrate: 1. CMOS
ROIC, 2. Patterned pixel electrodes (anode), 3. Hole transport layer, 4. CQD absorber layer, 5. Electron transport
layer, 6. Transparent top electrode (cathode), 7. Transparent dielectric layer. (Image: Emberion)
(a)
Power management and references
Bandgap
Bias
LDOs
Test structures
Temperature sensor
& ref pixels
Dphoto
ΔV= 0
V bias = constant
Pixel array and signal path
Pixel Array
Column/line drivers
Digital controls and interfaces
Digital (1.8V)
Programable sequencer
Registers
SPI
1.8V
32 BIT
CHIP ID
(e)
(d)
Sensor Front-end Board
VGA Image
Sensor
640×512
pixel
FPA
TEC
ROIC controls
28-pin metal
package
Application
processor
TEC control
TEC
driver
Diiferential
outputs
ADC
Real-time
processor
Interface
board
Camera Processing Board
SOC
FPGA
PGAs
M 4× HS
u
x
ADC
sync
Dphoto
V0C
(c)
OUTPUT
BUFFERS
EXT ADC
4×
channel
-
+
1=0
-
+
(b)
I
3
7
6
5
4
increases as a function of photogenerated
charge eventually reaching open-circuit
voltage in the case of sufficiently
long exposure time. The input impedance
of the pixel electronics is in the TΩ
range so that minimal charge leakage
occurs during exposure, whilst, between
exposure cycles, the photodiode is reset
by short-circuiting the photodiode stack
thus discharging any photogenerated
charge between successive frames. The
VGA imager reported here has been optimized
to operate in voltage-mode over a
wide range of exposure times achieving
above 400 fps for full VGA resolution
with minimum exposure time of 1 µs.
The input-referred read-out noise level at
the pixel front-end is ~180 µV. The signal
path gain from pixel electrode to ASIC
differential output is adjustable (0 to
29.5 dB) and currently optimized to
yield G ≈ 8 for pixel voltages 0 to 100 mV.
Looking beyond the work reported
here, our latest generation ROIC supports
up to 1.3 MPixel array size with
minimum pixel pitch of 10 µm, where
the dual-mode pixel front-end accommodates
for either voltage or current-mode
measurement, the latter with
reverse-biased stack and CTIA design.
Camera Design and IPP
The VS20 Core/Compact product was
Figure 2. (a) Simplified block diagram of modular read-out IC. (b) Reverse-bias current-mode measurement
principle. (c) Voltage-mode measurement principle. (d) Camera functional block diagram. (e) 3D CAD design
with electronics boards and hermetic sensor package. (Image: Emberion)
Image Sensor ROIC
The Emberion designed ROIC architecture
supports modularity and enables
functionalities for different types and
sizes of arrays and pixels according to
application requirements. The ROIC
contains a system-on-chip (SoC) solution
corresponding to the block diagram
presented in Figure 2(a). Here, the
sequencer controls the exposure and
reset times, trigger synchronization, and
other features such as HW-level regions
of interest (ROI). The ROIC is controlled
via the serial peripheral interface (SPI)
from a camera core. A base sequence is
pre-programmed into the ROIC's ROM
enabling image / video acquisition
16
immediately upon power-up. The
sequencer is re-programmable via SPI to
support more advanced sequences when
needed. Differential analog high-speed
buffers output the signal to an external
analog-to- digital converter (ADC) located
on the camera front-end board. The
image sensor ROIC reported here supports
VGA resolution with 20 um pixel
pitch and 15.0 × 12.4 mm2 overall imager
die size with IO-ring included.
The p-i-n type photodiode structures
can be read-out either in current-mode
(Figure 2(b)), where the photodiode is
typically reverse-biased, or in voltage-mode
(Figure 2(c)), where the forward-voltage
across the photodiode
mobilityengineeringtech.com
first demonstrated at Photonics West 2024
to complement Emberion's camera offering
with a form-factor optimized for system
integration. The camera solution
incorporates all necessary functionalities
for sensor readout, control, analog-to-digital
signal conversion, image pre-processing,
thermal control, power management
and GigE Vision interface capable of frame
rates up to and above 400 fps. Stable performance
over a wide operational temperature
range is ensured with a thermo-electric
cooling (TEC) element built in the
image sensor package. For the stand-alone
camera, the circuit boards are supplemented
by housing designed for efficient thermal
management and protection against
dust intrusion. The VS20 Core/Compact is
compatible with commercial lens systems
with a standard C-mount optical interface.
The back cover has power/trigger and RJ45
ethernet connectors.
The camera functional block diagram
is shown in Figure 2(d) and a 3D
Aerospace & Defense Technology, June 2024
http://mobilityengineeringtech.com
Aerospace & Defense Technology - June 2024

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